Responsibilities
1. Participation The implementation of the hardware acceleration project of the ByteDance data center, responsible for the development and debugging of the basic software stack of heterogeneous computing 2. Highly coordinated with the hardware R&D team to carry out integrated software and hardware development, including but not limited to Feature enablement and driver development , Performance tuning 3. Explore technical trends and industry practices in FPGA/ASIC/GPU/RISC-V, CXL and other fields, and demonstrate the value and feasibility of new technologies in byte-beating business scenarios.
Qualifications
1. Familiar with computer architecture, at least one in-depth understanding of X86, ARM, RISC-V, GPU four architectures, Understand its micro-architecture, main instruction set, etc. 2. Proficient in C/C++ and other development languages 3. Familiar with Linux KMD/UMD development framework, have actual high-performance driver development experience, and be familiar with SMMU/IOMMU/DMA/Interrupt/VFIO, etc. Relevant modules 4. In-depth understanding of the Linux kernel, at least read the source code of one major subsystem (scheduling, network, I/O, memory, storage, network, etc.), familiar with PCIe protocol and device drivers Linux kernel and user mode program fault location and profiling capabilities. Bonus items: 1. Familiar with mainstream hardware virtualization technology, in-depth understanding of at least one of CPU virtualization, memory virtualization, IO virtualization (VirtIO, device pass-through technology), DPDK, SPDK 2. Familiar with AI accelerator Runtime/ Inference/Training Framework, experience in actual development and performance optimization 3. Have a certain understanding of CXL and other memory consistency protocols and application scenarios, and experience in related heterogeneous memory architecture design 4. Heterogeneous computing platforms such as OpenCL and CUDA , Machine learning, big data technology, K8S technology, one or above has a certain understanding.